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ltc6417 1 6417f the ltc ? 6417 is a differential unity gain buffer that can drive a 50? load with extremely low noise and excellent linearity. it is well suited for driving high speed 14- and 16-bit pipeline adcs with input signals from dc to beyond 600mhz. differential input impedance is 18.5k?, allowing 1:4 and 1:8 transformers to be used at the input providing additional system gain in 50 systems. with no external biasing or gain setting components and a flow-through pinout, the ltc6417 is very easy to use. it can be dc-coupled and has a common mode output offset of C60mv. the ltc6417 input pins are internally biased to provide an output common mode voltage that is set by the voltage on the v cm pin for ac-coupled applications. supply current is typically 123ma and the ltc6417 operates on supply voltages ranging from 4.75v to 5.25v. power consumption can be reduced to 74ma via the pwradj pin. the ltc6417 also has a hardware shutdown feature which reduces current consumption to 24ma. the ltc6417 features fast, adjustable output voltage clamp - ing to help protect subsequent circuitry. the clhi pin sets the maximum swing, while a symmetric minimum swing is set up internally. ltc6417 v or pin will signal overrange when the clamps limit output voltage. the ltc6417 is packaged in a 20-lead 3mm 4mm qfn package. pinout is optimized for placement directly adjacent to linear technologys high speed 14- and 16-bit adcs. typical a pplica t ion descrip t ion 1.6 ghz low noise high linearity differential buffer/16-bit adc driver with fast clamp ltc6417 driving an ltc2209 16-bit adc at 140mhz if fea t ures a pplica t ions n 1.6ghz C3db small signal bandwidth n low distortion driving 50? load, 2.4v p-p out C100dbc/C69dbc hd2/hd3 at 140mhz C80dbc im3 and 46dbm oip3 at 140mhz C100dbc/C66dbc hd2/hd3 at 380mhz C68dbc im3 and 39dbm oip3 at 380mhz n 1.5nv/hz output noise n 4.3pa/hz input current noise n programmable high speed, fast recovery output clamping n 4.28v p-p maximum output swing on a 50 differential load n dc-coupled signal path n operates on single 4.75v to 5.25v supply n power: 615mw on 5v, can be reduced to 370mw , shutdown mode 120mw n 3mm 4mm 20-lead qfn package n differential adc driver n ccd buffer n cable driver n 50? buffer ltc6417 driving ltc2209 16-bit adc 32k point fft, f in = 140mhz, C1dbfs, pga = 0 l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. frequency (mhz) amplitude (dbfs) 6417 ta01b 0 80 403020 706050 10 0 ?20 ?30 ?10 ?50 ?60 ?40 ?70 ?80 ?100 ?110 ?90 ?120 hd2 = ?88dbc hd3 = ?94dbc sfdr = 88dbc snr = 75.4db see figure 1/table 1 1:4 balun f s = 153.6msps demo board dc1685a ?? pwradj gnd shdn clhi v or 6417 ta01a out + out ? 0.1f 5v 2.2f 3.3v v cm 2.2f 8 1,6, 11,16 3, 7,10, 17, 20, 21 5 12 15 14 2 9 19 18 10 10 r42 300 c45 18pf e3 75nh r43 300 1k r53 120 a in + a in ? pga = 0 ltc2209 in + v + in ? ltc6417 680pf clock (153.6mhz) 16 v cm c40 12pf c41 12pf e5 51nh c10 12pf c46 18pf e3 75nh r36 60.4 c43 27pf e1 51nh r12 60.4 c44 27pf e2 51nh 100 100 0.01f 0.01f t1 wbc4-14lb 4 6 3 2 1 50 + ?
ltc6417 2 6417f p in c on f igura t ion a bsolu t e maxi m u m r a t ings total supply voltage (v + to gnd) ............................. 5 .5v input current (clhi, v cm ) .................................... 10 ma input current (in + , in C ) ........................................ 3 0ma output current (out + , out C ) ............................. 10 0ma output current (v or ) ........................................... 10 ma operating temperature range (t c ) (note 2) .......................................... C4 0c to 105c specified temperature range (t c ) (note 3) .......................................... C4 0c to 105c storage temperature range .................. C 65c to 150c junction temperature (t jmax ) .............................. 150 c (note 1) 20 19 18 17 7 8 top view 21 gnd udc package 20-lead (3mm 4mm) plastic qfn 9 10 6 5 4 3 2 1 11 12 13 14 15 16 v + clhi gnd nc pwradj v + v + v cm v or nc shdn v + gnd out + out ? gnd gnd in + in ? gnd t jmax = 150c, v ja = 52c/w, v jc = 6.8c/w exposed pad (pin 21) is gnd, must be soldered to pcb o r d er i n f or m a t ion d c e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v + = 5v, gnd = 0v, no r load , c load = 6pf. v cm = 1.25v, clhi = v + , pwradj = v + , shdn = 0v unless otherwise noted. v incm is defined as (in + + in C )/2. v outcm is defined as (out + + out C )/2. v indiff is defined as (in + C in C ). v outdiff is defined as (out + C out C ). see dc test circuit schematic. symbol parameter conditions min typ max units input/output characteristics g diff differential gain v indiff = 1.2v differential l C0.15 C0.2 C0.1 0 0 db db tcg diff differential gain temperature coefficient l 0.0002 db/c v swingdiff differential output voltage swing v outdiff , v indiff = 2.3v l 4 3.3 4.28 v p-p v p-p v swingmin output voltage swing low single-ended measurement of out + , out C v indiff = 2.3v l 0.19 0.28 0.4 v v v swingmax output voltage swing high single-ended measurement of out + , out C v indiff = 2.3v l 2.25 2.05 2.33 v v lead free finish tape and reel part marking* package description temperature range ltc6417cudc#pbf ltc6417cudc#trpbf lfvn 20-lead (3mm w 4mm) plastic qfn 0c to 70c ltc6417iudc#pbf ltc6417iudc#trpbf lfvn 20-lead (3mm w 4mm) plastic qfn C40c to 105c (t c ) *temperature grades are identified by a label on the shipping container. consult ltc marketing for parts specified with wider operating temperature ranges. consult ltc marketing for information on lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ltc6417 3 6417f d c e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v + = 5v, gnd = 0v, no r load , c load = 6pf. v cm = 1.25v, clhi = v + , pwradj = v + , shdn = 0v unless otherwise noted. v incm is defined as (in + + in C )/2. v outcm is defined as (out + + out C )/2. v indiff is defined as (in + C in C ). v outdiff is defined as (out + C out C ). see dc test circuit schematic. symbol parameter conditions min typ max units i out output current drive (notes 1, 4) single-ended measurement of out + , out C l 100 ma v os differential input offset voltage in + = in C = 1.25v, v os = v outdiff /g diff l C3.2 C4 C0.1 3.2 4 mv mv tcv os differential input offset voltage drift l 1 v/c v iocm common mode offset voltage, input to output v outcm C v incm l C120 C140 C60 C10 0 mv mv ivr min input voltage range, in + , in C (minimum) (single-ended) defined by output voltage swing test l 0.1 v ivr max input voltage range in + , in C (maximum) (single-ended) defined by output voltage swing test l 2.4 v i b input bias current, in + , in C in + = in C = 1.25v l C13 C18 2 13 18 a a r indiff differential input resistance v indiff = 1.2v l 12 11 18.5 25 27.5 k k c indiff differential input capacitance 1 pf r incm input common mode resistance in + = in C = 0.65v to 1.85v l 5.8 5 9.25 13 15 k k cmrr common mode rejection ratio in + = in C = 0.65v to 1.85v, cmrr = (v outdiff /g diff /1.2v) l 63 60 91 db db r outdiff differential output resistance 3 e n input noise voltage density f = 100khz 1.5 nv/ hz i n input noise current density f = 100khz 4.3 pa/hz output common mode voltage control g cm v cm pin common mode gain v cm = 0.65v to 1.85v l 0.82 0.8 0.92 v/v v/v v incmdefault default input common mode voltage v incm . in + , in C , v cm pin floating l 1.15 1.1 1.25 1.35 1.4 v v v os (v cm C v incm ) offset voltage, v cm to v incm v cm C v incm , v cm = 1.25v l C85 C90 15 115 135 mv mv v outcmdefault default output common mode voltage inputs floating, v cm pin floating l 1.1 1 1.2 1.3 1.35 v v v os (v cm C v outcm ) offset voltage, v cm to v outcm v cm C v outcm , v cm = 1.25v l C50 C45 75 200 230 mv mv v outcmmin output common mode voltage range (minimum) v cm = 0.1v l 0.29 0.63 0.65 v v v outcmmax output common mode voltage range (maximum) v cm = 2.4v l 2 1.85 2.25 v v v cmdefault v cm pin default voltage l 1.15 1.1 1.25 1.35 1.4 v v r vcm v cm pin input resistance v cm = 0.65v to 1.85v l 2 1.9 2.7 3.4 3.7 k k c vcm v cm pin input capacitance 1 pf i bvcm v cm pin bias current v cm = 1.25v l C15 C27.5 1 15 27.5 a a
ltc6417 4 6417f symbol parameter conditions min typ max units dc clamping characteristics v clhidefault default output clamp voltage, high l 2.4 2.35 2.48 2.55 2.6 v v v os (clhi C v outcm ) offset voltage, clhi to v outcm l C60 C85 20 80 85 mv mv v os (cllo C v out ) offset voltage, cllo to v out v clhi = 2.0v, v cm = 1.25v, in + = 2.4v, in C = 0.1v l C100 C110 10 100 110 mv mv g lohi low side clamp gain with respect to clhi pin v clhi = 2.0v, v cm = 1.25v, in + = 2.4v, in C = 0.1v l C1.2 C1.25 C1 C0.8 C0.75 v/v v/v g locm low side clamp gain with respect to cm pin v clhi = 2.0v, v cm = 1.25v, in + = 2.4v, in C = 0.1v l 1.65 1.5 1.9 2.2 2.25 v/v v/v r clhi clhi pin input resistance v clhi = 1.5v to 2.5v l 3.4 3.1 4.8 5.7 6 k k ib clhi clhi pin bias current v clhi = 2.5v l C12 C12.5 3 18 18.5 a a power supply v s supply voltage range l 4.75 5.25 v i s supply current l 100 95 123 140 145 ma ma psrr power supply rejection ratio v s = 4.75v to 5.25v l 65 63 72 db db shdn pin is shdn shutdown current v shdn = 5v l 17 15 24 29 35 ma ma v shdndefault default shutdown voltage l 0.1 v v il,shdn shdn input low voltage l 2 v v ih,shdn shdn input high voltage l 3.5 v i il,shdn shdn input low current shdn = 0v l C1.6 C2 0 1.6 2 a a i ih,shdn shdn input high current shdn = 5v l 275 250 380 450 475 a a c shdn shdn pin input capacitance 1 pf r shdn shdn pin input resistance shdn = 2.5v to 5v l 6 5 10.5 14 15 k k pwradj pin v pwradjdefault default pwradj voltage pwradj floating 1.5 1.45 1.65 1.8 1.85 v v is l supply low current pwradj = 0v l 45 40 74 105 110 ma ma i il, pwradj pwradj input low current pwradj = 0v l C145 C165 C120 C80 C75 a a i ih, pwradj pwradj input high current pwradj = 5v l 210 200 240 290 300 a a c pwradj pwradj pin input capacitance 1 pf d c e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v + = 5v, gnd = 0v, no r load , c load = 6pf. v cm = 1.25v, clhi = v + , pwradj = v + , shdn = 0v unless otherwise noted. v incm is defined as (in + + in C )/2. v outcm is defined as (out + + out C )/2. v indiff is defined as (in + C in C ). v outdiff is defined as (out + C out C ). see dc test circuit schematic.
ltc6417 5 6417f ac e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v + = 5v unless otherwise noted, gnd = 0v, r load = 500,c load = 6pf. v cm = 1.25v, clhi = v + , pwradj = v cc , shdn = 0v unless otherwise noted. v incm is defined as (in + + in C )/2. v outcm is defined as (out + + out C )/2. v indiff is defined as (in + C in C ). v outdiff is defined as (out + C out C ). see dc test circuit schematic. symbol parameter conditions min typ max units differential ac characteristics C3dbbw C3db bandwidth 200mv p-p,out differential 1.6 ghz 0.1dbbw 0.1db bandwidth 200mv p-p,out differential 0.18 ghz 0.5dbbw 0.5db bandwidth 200mv p-p,out differential 0.45 ghz 1/f 1/f noise corner 25 khz sr slew rate differential 10 v/ns t s1% 1% settling time 2v p-p,out 0.8 ns t off shutdown time shdn = 0v to 5v 40 ns t on enable time shdn = 5v to 0v 15 ns t pwradj,off pwradj off time pwradj = 5v to 0v 10 ns t pwradj,on pwradj on time pwradj = 0v to 5v 5 ns t cl,off 10% clamp release time clhi = 1.5v, v cm = 1.25v, in + = 1.625v to 1.25v, in C = 1.25v to 0.875v 1 ns t cl,on 10% clamp engage time clhi = 1.5v, v cm = 1.25v, in + = 1.25v to 1.625v, in C = 1.25v to 0.875v 5 ns common mode ac characteristics (v cm pin) C3dbbw v cm pin small signal C3db bw v cm = 0.1v p-p , measured single-ended at output 10 mhz sr cm common mode slew rate measured single-ended at output 2 v/s overrange ac characteristics (v or pin) C3dbbw v or pin small signal C3db bw v or = 0.1v p-p , clhi = 2v, in + = 2.4v, in C = 0.1v, r vor = 1k, measured single-ended at output 200 mhz sr vor overrange slew rate measured single-ended at output 40 v/s ac clamping characteristics t ovdr overdrive recovery time 1.9v p-p,out 2 ns symbol parameter conditions min typ max units r pwradj pwradj pin input resistance pwradj = 2.5v to 5.0v l 10.5 10 14.5 19 20 k k v or pin v or(hi) maximum voltage on v or pin v cl = 5.0v, v cm = 1.25v l 3.25 3.2 3.35 3.55 3.6 v v i or (default) default pull-down current on v or pin v cl = 50v, v cm = 1.25v l C900 C1150 C770 C650 C500 a a i or(max) maximum pull-down current both clamps are active v cl = 2.0v, v cm = 1.25v, in + = 2.4v, in C = 0.1v l 1 1.5 2 a a d c e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v + = 5v, gnd = 0v, no r load , c load = 6pf. v cm = 1.25v, clhi = v + , pwradj = v + , shdn = 0v unless otherwise noted. v incm is defined as (in + + in C )/2. v outcm is defined as (out + + out C )/2. v indiff is defined as (in + C in C ). v outdiff is defined as (out + C out C ). see dc test circuit schematic.
ltc6417 6 6417f symbol parameter conditions min typ max units ac linearity 10mhz signal hd3 third harmonic distortion v outdiff = 2.4v p-p , r l = 50 v outdiff = 2.4v p-p C89 C93 dbc dbc im3 third order intermodulation distortion v outdiff = 2.4v p-p , r l = 50 v outdiff = 2.4v p-p C100 C110 dbc dbc oip3 output third order intercept v outdiff = 2.4v p-p , r l = 50 56 dbm p1db output 1db compression point 16.1 dbm 70mhz signal hd3 third harmonic distortion v outdiff = 2.4v p-p , r l = 50 v outdiff = 2.4v p-p C74 C77 dbc dbc im3 third order intermodulation distortion v outdiff = 2.4v p-p , r l = 50 v outdiff = 2.4v p-p C86 C96 dbc dbc oip3 output third order intercept v outdiff = 2.4v p-p , r l = 50 48 dbm p1db output 1db compression point 15.8 dbm 140mhz signal hd3 third harmonic distortion v outdiff = 2.4v p-p , r l = 50 v outdiff = 2.4v p-p C69 C73 dbc dbc im3 third order intermodulation distortion v outdiff = 2.4v p-p , r l = 50 v outdiff = 2.4v p-p C80 C91 dbc dbc oip3 output third order intercept v outdiff = 2.4v p-p , r l = 50 46 dbm p1db output 1db compression point 15.8 dbm 200mhz signal hd3 third harmonic distortion v outdiff = 2.4v p-p , r l = 50 v outdiff = 2.4v p-p C68 C71 dbc dbc im3 third order intermodulation distortion v outdiff = 2.4v p-p , r l = 50 v outdiff = 2.4v p-p C78 C87 dbc dbc oip3 output third order intercept v outdiff = 2.4v p-p , r l = 50 44 dbm p1db output 1db compression point 15.8 dbm 240mhz signal hd3 third harmonic distortion v outdiff = 2.4v p-p , r l = 50 v outdiff = 2.4v p-p C67 C70 dbc dbc im3 third order intermodulation distortion v outdiff = 2.4v p-p , r l = 50 v outdiff = 2.4v p-p C76 C85 dbc dbc oip3 output third order intercept v outdiff = 2.4v p-p , r l = 50 43 dbm p1db output 1db compression point 15.7 dbm 300mhz signal hd3 third harmonic distortion v outdiff = 2.4v p-p , r l = 50 v outdiff = 2.4v p-p C66 C69 dbc dbc ac e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v + = 5v unless otherwise noted, gnd = 0v, r load = 500,c load = 6pf. v cm = 1.25v, clhi = v + , pwradj = v cc , shdn = 0v unless otherwise noted. v incm is defined as (in + + in C )/2. v outcm is defined as (out + + out C )/2. v indiff is defined as (in + C in C ). v outdiff is defined as (out + C out C ). see dc test circuit schematic.
ltc6417 7 6417f note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc6417c/ltc6417i is guaranteed functional over the case temperature operating range of C40c to 105c. jc = 6.8c/w. note 3: the ltc6417c is guaranteed to meet specified performance from 0c to 70c. it is designed, characterized and expected to meet specified performance from C40c and 105c case temperature range but is not tested or qa sampled at these temperatures. the lt6417i is guaranteed to meet specified performance from C40c to 105c case temperature range. note 4: this parameter is pulse tested. ac e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v + = 5v unless otherwise noted, gnd = 0v, r load = 500,c load = 6pf. v cm = 1.25v, clhi = v + , pwradj = v cc , shdn = 0v unless otherwise noted. v incm is defined as (in + + in C )/2. v outcm is defined as (out + + out C )/2. v indiff is defined as (in + C in C ). v outdiff is defined as (out + C out C ). see dc test circuit schematic. symbol parameter conditions min typ max units im3 third order intermodulation distortion v outdiff = 2.4v p-p , r l = 50 v outdiff = 2.4v p-p C73 C79 dbc dbc oip3 output third order intercept v outdiff = 2.4v p-p , r l = 50 41 dbm p1db output 1db compression point 15.6 dbm 380mhz signal hd3 third harmonic distortion v outdiff = 2.4v p-p , r l = 50 v outdiff = 2.4v p-p C66 C68 dbc dbc im3 third order intermodulation distortion v outdiff = 2.4v p-p , r l = 50 v outdiff = 2.4v p-p C68 C77 dbc dbc oip3 output third order intercept v outdiff = 2.4v p-p , r l = 50 36 39 dbm p1db output 1db compression point 15.3 dbm 400mhz signal hd3 third harmonic distortion v outdiff = 2.4v p-p , r l = 50 v outdiff = 2.4v p-p C65 C68 dbc dbc im3 third order intermodulation distortion v outdiff = 2.4v p-p , r l = 50 C68 dbc oip3 output third order intercept v outdiff = 2.4v p-p , r l = 50 39 dbm p1db output 1db compression point 15.3 dbm 500mhz signal hd3 third harmonic distortion v outdiff = 2.4v p-p , r l = 50 v outdiff = 2.4v p-p C65 C67 dbc dbc im3 third order intermodulation distortion v outdiff = 2.4v p-p , r l = 50 C64 dbc oip3 output third order intercept v outdiff = 2.4v p-p , r l = 50 37 dbm p1db output 1db compression point 15.0 dbm 600mhz signal hd3 third harmonic distortion v outdiff = 2.4v p-p , r l = 50 C60 dbc im3 third order intermodulation distortion v outdiff = 2.4v p-p , r l = 50 C58 dbc oip3 output third order intercept v outdiff = 2.4v p-p , r l = 50 34 dbm p1db output 1db compression point 14.7 dbm 700mhz signal hd3 third harmonic distortion v outdiff = 2.4v p-p , r l = 50 C55 dbc im3 third order intermodulation distortion v outdiff = 2.4v p-p , r l = 50 C52 dbc oip3 output third order intercept v outdiff = 2.4v p-p , r l = 50 31 dbm p1db output 1db compression point 14.2 dbm
ltc6417 8 6417f typical p er f or m ance c harac t eris t ics hd3 at 70mhz vs v cm over v + hd3 at 70mhz vs pwradj over temperature hd3 at 30mhz vs v cm over v + hd3 at 30mhz vs pwradj over temperature hd3 at 70mhz vs v cm over temperature hd3 at 30mhz vs v cm over temperature v cm (v) hd3 (dbc) 6417 g01 0.85 1.55 1.65 1.45 1.25 1.35 1.151.050.95 ?50 ?60 ?80 ?70 ?90 ?100 105c 85c 25c ?40c p out = 11dbm v cm (v) hd3 (dbc) 6417 g02 0.85 1.55 1.65 1.45 1.25 1.35 1.151.050.95 ?50 ?60 ?80 ?70 ?90 ?100 v + = 4.75v v + = 5.0v v + = 5.25v p out = 11dbm pwradj (v) hd3 (dbc) 6417 g03 0 3.5 5 3 4.54 2 2.5 1.510.5 ?50 ?60 ?80 ?70 ?90 ?100 105c 85c 25c ?40c p out = 11dbm v cm (v) hd3 (dbc) 6417 g04 0.85 1.55 1.65 1.45 1.25 1.35 1.151.050.95 ?45 ?55 ?75 ?65 ?85 ?95 p out = 11dbm ?40c 25c 105c 85c v cm (v) hd3 (dbc) 6417 g05 0.85 1.55 1.65 1.45 1.25 1.35 1.151.050.95 ?50 ?60 ?80 ?70 ?90 ?100 v + = 4.75v v + = 5.0v v + = 5.25v p out = 11dbm pwradj (v) hd3 (dbc) 6417 g06 0 4.5 543 3.5 2.521.510.5 ?50 ?60 ?80 ?70 ?90 ?100 ?40c 25c 105c 85c p out = 11dbm hd3 at 140mhz vs v cm over v + hd3 at 140mhz vs pwradj over temperature hd3 at 140mhz vs v cm over temperature v cm (v) hd3 (dbc) 6417 g08 0.85 1.55 1.65 1.45 1.25 1.35 1.151.050.95 ?40 ?50 ?70 ?60 ?80 ?90 v + = 4.75v v + = 5.0v v + = 5.25v p out = 11dbm v cm (v) hd3 (dbc) 6417 g07 0.85 1.55 1.65 1.45 1.25 1.35 1.151.050.95 ?40 ?50 ?70 ?60 ?80 ?90 ?40c 25c p out = 11dbm 105c 85c pwradj (v) hd3 (dbc) 6417 g09 0 3.5 5 3 4.54 2 2.5 1.510.5 ?40 ?50 ?70 ?60 ?80 ?90 ?40c 25c 85c 105c p out = 11dbm
ltc6417 9 6417f typical p er f or m ance c harac t eris t ics hd3 at 240mhz vs v cm over v + hd3 at 240mhz vs pwradj over temperature hd3 at 240mhz vs v cm over temperature v cm (v) hd3 (dbc) 6417 g10 0.85 1.55 1.65 1.45 1.25 1.35 1.151.050.95 ?35 ?45 ?65 ?55 ?75 ?85 ?40c 25c p out = 11dbm 105c 85c v cm (v) hd3 (dbc) 6417 g11 0.85 1.55 1.65 1.45 1.25 1.35 1.151.050.95 ?40 ?50 ?70 ?60 ?80 ?90 v + = 4.75v v + = 5.0v v + = 5.25v p out = 11dbm pwradj (v) hd3 (dbc) 6417 g12 0 3.5 5 3 4.54 2 2.5 1.510.5 ?40 ?50 ?70 ?60 ?80 ?90 ?40c 25c 105c 85c p out = 11dbm hd3 at 380mhz vs v cm over v + hd3 at 380mhz vs pwradj over temperature hd3 at 380mhz vs v cm over temperature v cm (v) hd3 (dbc) 6417 g13 0.85 1.55 1.65 1.45 1.25 1.35 1.151.050.95 ?25 ?35 ?55 ?45 ?65 ?75 ?40c 25c 85c p out = 11dbm 105c v cm (v) hd3 (dbc) 6417 g14 0.85 1.55 1.65 1.45 1.25 1.35 1.151.050.95 ?30 ?40 ?60 ?50 ?70 ?80 v + = 4.75v v + = 5.0v v + = 5.25v p out = 11dbm pwradj (v) hd3 (dbc) 6417 g15 0 3.5 5 3 4.54 2 2.5 1.510.5 ?30 ?40 ?60 ?50 ?70 ?80 ?40c 25c 85c 105c p out = 11dbm hd3 at 500mhz vs v cm over v + hd3 at 500mhz vs pwradj over temperature hd3 at 500mhz vs v cm over temperature v cm (v) hd3 (dbc) 6417 g16 0.85 1.55 1.65 1.45 1.25 1.35 1.151.050.95 ?30 ?40 ?60 ?50 ?70 ?80 ?40c 25c 105c p out = 11dbm 85c v cm (v) hd3 (dbc) 6417 g17 0.85 1.55 1.65 1.45 1.25 1.35 1.151.050.95 ?30 ?40 ?60 ?50 ?70 ?80 p out = 11dbm v + = 4.75v v + = 5.0v v + = 5.25v pwradj (v) hd3 (dbc) 6417 g18 0 3.5 5 3 4.54 2 2.5 1.510.5 ?30 ?40 ?60 ?50 ?70 ?80 ?40c 85c 25c 105c p out = 11dbm
ltc6417 10 6417f typical p er f or m ance c harac t eris t ics hd3 at 700mhz vs v cm over v + hd3 at 700mhz vs pwradj over temperature hd3 at 600mhz vs v cm over v + hd3 at 600mhz vs pwradj over temperature hd3 at 700mhz vs v cm over temperature hd3 at 600mhz vs v cm over temperature oip3 at 30mhz vs v cm over v + oip3 at 30mhz vs pwradj over temperature oip3 at 30mhz vs v cm over temperature v cm (v) hd3 (dbc) 6417 g19 0.85 1.55 1.65 1.45 1.25 1.35 1.151.050.95 ?30 ?40 ?60 ?50 ?70 ?80 25c ?40c 85c 105c p out = 11dbm v cm (v) hd3 (dbc) 6417 g20 0.85 1.55 1.65 1.45 1.25 1.35 1.151.050.95 ?30 ?40 ?60 ?50 ?70 ?80 v + = 4.75v v + = 5.0v v + = 5.25v p out = 11dbm pwradj (v) hd3 (dbc) 6417 g21 0 3.5 5 3 4.54 2 2.5 1.510.5 ?30 ?40 ?60 ?50 ?70 ?80 ?40c 25c 85c 105c p out = 11dbm v cm (v) hd3 (dbc) 6417 g22 0.85 1.55 1.65 1.45 1.25 1.35 1.151.050.95 ?30 ?40 ?60 ?50 ?70 ?80 ?40c 25c 105c 85c p out = 11dbm v cm (v) hd3 (dbc) 6417 g23 0.85 1.55 1.65 1.45 1.25 1.35 1.151.050.95 ?30 ?40 ?60 ?50 ?70 ?80 p out = 11dbm v + = 4.75v v + = 5.0v v + = 5.25v pwradj (v) hd3 (dbc) 6417 g24 0 3.5 5 3 4.54 2 2.5 1.510.5 ?30 ?40 ?60 ?50 ?70 ?80 ?40c 25c 85c 105c p out = 11dbm v cm (v) oip3 (dbm) 6417 g25 0.85 1.55 1.65 1.45 1.25 1.35 1.151.050.95 55 50 40 45 30 25 35 85c 105c 25c ?40c p out = 5dbm/tone ?freq = 1mhz v cm (v) oip3 (dbm) 6417 g26 0.85 1.55 1.65 1.45 1.25 1.35 1.151.050.95 55 50 40 45 30 25 35 v + = 4.75v v + = 5.0v v + = 5.25v p out = 5dbm/tone ?freq = 1mhz pwradj (v) oip3 (dbm) 6417 g27 0 3.5 5 3 4.54 2 2.5 1.510.5 55 50 40 45 30 35 25 ?40c 105c 85c 25c p out = 5dbm/tone ?freq = 1mhz
ltc6417 11 6417f typical p er f or m ance c harac t eris t ics oip3 at 70mhz vs v cm over v + oip3 at 70mhz vs pwradj over temperature oip3 at 70mhz vs v cm over temperature oip3 at 100mhz vs v cm over v + oip3 at 100mhz vs pwradj over temperature oip3 at 100mhz vs v cm over temperature oip3 at 140mhz vs v cm over v + oip3 at 140mhz vs pwradj over temperature oip3 at 140mhz vs v cm over temperature v cm (v) oip3 (dbm) 6417 g28 0.85 1.55 1.65 1.45 1.25 1.35 1.151.050.95 55 50 40 45 30 25 35 ?40c 25c 85c 105c p out = 5dbm/tone ?freq = 1mhz v cm (v) oip3 (dbm) 6417 g29 0.85 1.55 1.65 1.45 1.25 1.35 1.151.050.95 55 50 40 45 30 25 35 v + = 4.75v v + = 5.0v v + = 5.25v p out = 5dbm/tone ?freq = 1mhz pwradj (v) oip3 (dbm) 6417 g30 0 3.5 5 3 4.54 2 2.5 1.510.5 55 50 40 45 30 35 25 ?40c 105c 25c 85c p out = 5dbm/tone ?freq = 1mhz v cm (v) oip3 (dbm) 6417 g31 0.85 1.55 1.65 1.45 1.25 1.35 1.151.050.95 55 50 40 45 30 25 35 ?40c 25c 105c 85c p out = 5dbm/tone ?freq = 1mhz v cm (v) oip3 (dbm) 6417 g32 0.85 1.55 1.65 1.45 1.25 1.35 1.151.050.95 55 50 40 45 30 25 35 v + = 4.75v v + = 5.0v v + = 5.25v p out = 5dbm/tone ?freq = 1mhz pwradj (v) oip3 (dbc) 6417 g33 0 3.5 5 3 4.54 2 2.5 1.510.5 55 50 40 45 30 35 25 25c ?40c 105c 85c p out = 5dbm/tone ?freq = 1mhz v cm (v) oip3 (dbm) 6417 g34 0.85 1.55 1.65 1.45 1.25 1.35 1.151.050.95 55 50 40 45 30 25 35 ?40c 105c 25c 85c p out = 5dbm/tone ?freq = 1mhz v cm (v) oip3 (dbm) 6417 g35 0.85 1.55 1.65 1.45 1.25 1.35 1.151.050.95 55 50 40 45 30 25 35 v + = 4.75v v + = 5.0v v + = 5.25v p out = 5dbm/tone ?freq = 1mhz pwradj (v) oip3 (dbc) 6417 g36 0 3.5 5 3 4.54 2 2.5 1.510.5 55 50 40 45 30 35 25 105c 85c 25c ?40c p out = 5dbm/tone ?freq = 1mhz
ltc6417 12 6417f typical p er f or m ance c harac t eris t ics oip3 at 240mhz vs v cm over v + oip3 at 240mhz vs pwradj over temperature oip3 at 240mhz vs v cm over temperature oip3 at 380mhz vs v cm over v + oip3 at 380mhz vs pwradj over temperature oip3 at 380mhz vs v cm over temperature oip3 at 500mhz vs v cm over v + oip3 at 500mhz vs pwradj over temperature oip3 at 500mhz vs v cm over temperature v cm (v) oip3 (dbm) 6417 g37 0.85 1.55 1.65 1.45 1.25 1.35 1.151.050.95 50 45 35 40 25 20 30 ?40c 105c 85c 25c p out = 5dbm/tone ?freq = 1mhz v cm (v) oip3 (dbm) 6417 g38 0.85 1.55 1.65 1.45 1.25 1.35 1.151.050.95 55 50 40 45 30 25 35 v + = 4.75v v + = 5.0v v + = 5.25v p out = 5dbm/tone ?freq = 1mhz pwradj (v) oip3 (dbc) 6417 g39 0 3.5 5 3 4.54 2 2.5 1.510.5 55 50 40 45 30 35 25 ?40c 25c 105c 85c p out = 5dbm/tone ?freq = 1mhz v cm (v) oip3 (dbm) 6417 g40 0.85 1.55 1.65 1.45 1.25 1.35 1.151.050.95 50 45 35 40 25 20 30 ?40c 105c 25c 85c p out = 5dbm/tone ?freq = 1mhz v cm (v) oip3 (dbm) 6417 g41 0.85 1.55 1.65 1.45 1.25 1.35 1.151.050.95 55 50 40 45 30 25 35 v + = 4.75v v + = 5.0v v + = 5.25v p out = 5dbm/tone ?freq = 1mhz pwradj (v) oip3 (dbc) 6417 g42 0 3.5 5 3 4.54 2 2.5 1.510.5 55 50 40 45 30 35 25 ?40c 105c 25c 85c p out = 5dbm/tone ?freq = 1mhz v cm (v) oip3 (dbm) 6417 g43 0.85 1.55 1.65 1.45 1.25 1.35 1.151.050.95 50 45 35 40 25 20 30 ?40c 105c 85c 25c p out = 5dbm/tone ?freq = 1mhz v cm (v) oip3 (dbm) 6417 g44 0.85 1.55 1.65 1.45 1.25 1.35 1.151.050.95 50 45 35 40 25 20 30 v + = 4.75v v + = 5.0v v + = 5.25v p out = 5dbm/tone ?freq = 1mhz pwradj (v) oip3 (dbc) 6417 g45 0 3.5 5 3 4.54 2 2.5 1.510.5 50 45 35 40 25 30 20 ?40c 25c 105c 85c p out = 5dbm/tone ?freq = 1mhz
ltc6417 13 6417f typical p er f or m ance c harac t eris t ics oip3 at 600mhz vs v cm over v + oip3 at 600mhz vs pwradj over temperature oip3 at 600mhz vs v cm over temperature oip3 at 700mhz vs v cm over v + oip3 at 700mhz vs pwradj over temperature oip3 at 700mhz vs v cm over temperature supply current vs supply voltage supply current vs pwradj output 1db compression vs frequency and supply voltage v cm (v) oip3 (dbm) 6417 g46 0.85 1.55 1.65 1.45 1.25 1.35 1.151.050.95 45 40 30 35 20 15 25 ?40c 105c 25c 85c p out = 5dbm/tone ?freq = 1mhz v cm (v) oip3 (dbm) 6417 g47 0.85 1.55 1.65 1.45 1.25 1.35 1.151.050.95 45 40 30 35 20 15 25 v + = 4.75v v + = 5.0v v + = 5.25v p out = 5dbm/tone ?freq = 1mhz pwradj (v) oip3 (dbc) 6417 g48 0 3.5 5 3 4.54 2 2.5 1.510.5 45 40 30 35 20 25 15 ?40c 105c 85c 25c p out = 5dbm/tone ?freq = 1mhz v cm (v) oip3 (dbm) 6417 g49 0.85 1.55 1.65 1.45 1.25 1.35 1.151.050.95 45 40 30 35 20 15 25 ?40c 105c 25c 85c p out = 5dbm/tone ?freq = 1mhz v cm (v) oip3 (dbm) 6417 g50 0.85 1.55 1.65 1.45 1.25 1.35 1.151.050.95 45 40 30 35 20 15 25 v + = 4.75v v + = 5.0v v + = 5.25v p out = 5dbm/tone ?freq = 1mhz pwradj (v) oip3 (dbc) 6417 g51 0 3.5 5 3 4.54 2 2.5 1.510.5 45 40 30 35 20 25 15 ?40c 105c 25c 85c p out = 5dbm/tone ?freq = 1mhz frequency (mhz) p1 db compression (dbm) 6417 g52 100 600 700 500 300 400 200 20 16 18 12 10 14 v + = 5.25v v + = 5.0v v + = 4.75v supply voltage (v) supply current (ma) 6417 g53 0 54 2 3 1 140 100 120 40 60 20 0 80 pwradj (v) supply current (ma) 6417 g54 0 3.5 5 3 4.54 2 2.5 1.510.5 130 120 100 110 80 90 70
ltc6417 14 6417f typical p er f or m ance c harac t eris t ics differential input return loss (s11) vs frequency differential reverse isolation (s12) vs frequency differential forward gain (s21) vs frequency differential output return loss (s22) vs frequency ltc6417 driving ltc2209 16-bit adc, 32k point fft, f in = 69.5mhz, C1dbfs, pga = 0 small signal transient response, falling edge small signal transient response, rising edge overdrive recovery and overrange response frequency (mhz) s11 (db) 6417 g59 10 1000 100 0 ?20 ?30 ?10 ?40 r = 23.7 r = 0 demo board dc1660b frequency (mhz) s12 (db) 6417 g60 10 1000 100 ?60 ?100 ?80 ?120 r = 0 r = 23.7 demo board dc1660b frequency (mhz) s21 (db) 6417 g61 10 1000 100 10 5 ?5 0 ?10 r = 0 r = 23.7 demo board dc1660b frequency (mhz) s22 (db) 6417 g62 10 1000 100 0 ?20 ?30 ?10 ?40 r = 23.7 r = 0 demo board dc1660b frequency (mhz) amplitude (dbfs) 6417 g63 0 80 403020 706050 10 0 ?20 ?30 ?10 ?50 ?60 ?40 ?70 ?80 ?100 ?110 ?90 ?120 hdr = ?92dbc hd3 = ?86dbc sfdr = 86dbc snr = 76.2db see figure 1/table 1 1:4 balun f s = 153.6msps demo board dc1685a 2 3 1 small signal transient response, falling edge with input 1.25ns/div 6417 g55 62.5mv/ div 1.25ns/div 6417 g56 62.5mv/ div 20mv/ div 1.25ns/div 6417 g57 62.5mv/ div 10ns/div 6417 g58 10mv/ div 600mv/ div
ltc6417 15 6417f typical p er f or m ance c harac t eris t ics ltc6417 driving ltc2209 16-bit adc, 32k point fft, f in = 69.5mhz and 70.5mhz, C7dbfs/tone, pga = 0 ltc6417 driving ltc2209 16-bit adc, 64k point fft, f in = 140mhz, C1dbfs, pga = 0 ltc6417 driving ltc2209 16-bit adc, 64k point fft, f in = 270mhz, C1dbfs, pga = 0 ltc6417 driving ltc2209 16-bit adc, 64k point fft, f in = 380mhz, C1dbfs, pga = 0 frequency (mhz) amplitude (dbfs) 6417 g64 0 80 403020 706050 10 0 ?20 ?30 ?10 ?50 ?60 ?40 ?70 ?80 ?100 ?110 ?90 ?120 hd2 = ?88dbc hd3 = ?94dbc sfdr = 88dbc snr = 75.4db see figure 1/table 1 1:4 balun f s = 153.6msps demo board dc1685a 2 3 1 frequency (mhz) amplitude (dbfs) 6417 g66 0 80 403020 706050 10 0 ?20 ?30 ?10 ?50 ?60 ?40 ?70 ?80 ?100 ?110 ?90 ?120 hd2 = ?65dbc hd3 = ?74dbc sfdr = 65dbc snr = 71.0db see figure 1/table 1 1:4 balun f s = 153.6msps demo board dc1685a 2 3 1 frequency (mhz) amplitude (dbfs) 6417 g67 0 80 403020 706050 10 0 ?20 ?30 ?10 ?50 ?60 ?40 ?70 ?80 ?100 ?110 ?90 ?120 im3 = ?85dbc see figure 1/table 1 1:4 balun f s = 153.6msps demo board dc1685a frequency (mhz) amplitude (dbfs) 6417 g68 0 80 403020 706050 10 0 ?20 ?30 ?10 ?50 ?60 ?40 ?70 ?80 ?100 ?110 ?90 ?120 im3 = ?80dbc see figure 1/table 1 1:4 balun f s = 153.6msps demo board dc1685a frequency (mhz) amplitude (dbfs) 6417 g65 0 80 403020 706050 10 0 ?20 ?30 ?10 ?50 ?60 ?40 ?70 ?80 ?100 ?110 ?90 ?120 hd2 = ?81dbc hd3 = ?80dbc sfdr = 80dbc snr = 73.3db see figure 1/ table 1 1:4 balun f s = 153.6msps demo board dc1685a 2 3 1 frequency (mhz) amplitude (dbfs) 6417 g69 0 80 403020 706050 10 0 ?20 ?30 ?10 ?50 ?60 ?40 ?70 ?80 ?100 ?110 ?90 ?120 im3 = ?75dbc see figure 1/ table 1 1:4 balun f s = 153.6msps demo board dc1685a ltc6417 driving ltc2209 16-bit adc, 64k point fft, f in = 139.5mhz and 140mhz, C7dbfs/tone, pga = 0 ltc6417 driving ltc2209 16-bit adc, 64k point fft, f in = 269.5mhz and 270.5mhz, C7dbfs/tone, pga = 0 ltc6417 driving ltc2209 16-bit adc, 64k point fft, f in = 379.5mhz and 380.5mhz, C7dbfs/tone, pga = 0 frequency (mhz) amplitude (dbfs) 6417 g70 0 80 403020 706050 10 0 ?20 ?30 ?10 ?50 ?60 ?40 ?70 ?80 ?100 ?110 ?90 ?120 im3 = ?72dbc see figure 1/table 1 1:4 balun f s = 153.6msps demo board dc1685a input referred noise voltage vs frequency and noise figure for the dc1660b with 1:4 input balun input referred noise voltage vs frequency and noise figure for the dc1660b with 1:1 input balun frequency (mhz) input referred noise voltage (nv/ hz) noise figure (db) 6417 g71 0.001 0.10.01 1k100101 28 24 4 8 20 16 12 0 28 24 4 8 20 16 12 0 noise figure pwradj = 5v noise figure pwradj = 0v noise density pwradj = 5v noise density pwradj = 0v frequency (mhz) input referred noise voltage (nv/ hz) noise figure (db) 6417 g72 0.001 0.10.01 1k100101 24 4 8 20 16 12 0 24 4 8 20 16 12 0 noise figure pwradj = 5v noise figure pwradj = 0v noise density pwradj = 5v noise density pwradj = 0v
ltc6417 16 6417f p in func t ions v + (pins 1, 6, 11, 16): positive power supply. typically 5v. split supplies are possible as long as the voltage between v + and gnd is 4.75v to 5.25v. bypass capacitors of 680pf and 0.1f as close to the part as possible should be used between the supplies. clhi (pin 2): high side clamp voltage. the voltage ap- plied to the clhi pin defines the upper voltage limit of the out + and out C pins. this voltage should be set at least 300mv above the upper voltage range of the adc. on a 5v supply, the clhi pin will float to a 2.5v default voltage. clhi has a thevenin equivalent of approximately 4.8k? and can be overdriven by an external voltage. the clhi pin should be bypassed with a high quality ceramic bypass capacitor of at least 0.01f. gnd (pins 3, 7, 10, 17, 20, exposed pad pin 21): nega- tive power supply. normally tied to ground. all pins and the exposed pad must be tied to the same voltage. gnd may be tied to a voltage other than ground as long as the voltage between v + and gnd is 4.75v to 5.25v. if the gnd pins are not tied to ground, bypass each with 680pf and 0.1f capacitors as close to the package as possible. the exposed pad must be soldered to the printed circuit board ground plane for good heat transfer. nc (pins 4, 13): no connection. these pins are not con - nected internally. pwradj (pin 5): power adjust voltage. the voltage applied to this pin scales the bias current internal to the ltc6417. the pwradj pin will float to a 1.6v default voltage. pwradj has a thevenin equivalent resistance of approximately 14.5k and can be overdriven by an external voltage. the pwradj pin should be bypassed with a high quality ceramic bypass capacitor of at least 0.01f. in + , in C (pin 8, pin 9): non-inverting and inverting input pins of the buffer, respectively. these pins are high imped - ance, approximately 9.5k. if ac-coupled, these pins will self bias to the voltage applied to the v cm pin. shdn (pin 12): this pin puts the ltc6417 in sleep mode when pulled high. if no voltage is applied to the shdn pin, it floats down to the same potential as gnd. v or (pin 14): overrange output. this pin, by default at 3.4v, will be pulled down to gnd, when one or both input signals go beyond the minimum or maximum swing set by the clhi and v cm pins. v cm (pin 15): this pin sets the output common mode volt- age seen at out + and out C by driving in + and in C through a buffer with a high output resistance of 9.5k. the v cm pin has a thevenin equivalent resistance of approximately 2.7k and can be overdriven by an external voltage. if no voltage is applied to v cm , it will float to a default voltage of approximately 1.25v on a 5v supply. the v cm pin should be bypassed with a high quality ceramic bypass capacitor of at least 0.01f. out C , out + (pin 18, pin 19): outputs.
ltc6417 17 6417f d c tes t c ircui t s che m a t ic 19 15 2 8 9 5 3, 7, 10, 17, 20, 21 12 18 14 c load v + v + 1, 6, 11, 16 out ? shdn 6417 tc out + out ? out + r load v cm v cm in + in + clhi clhi pwradj pwradj in ? in ? ltc6417 v indiff = in + ? in ? in + + in ? 2 v incm = v outdiff = out + ? out ? out + + out ? 2 v outcm = v or v or b lock diagra m ltc6417 simplified schematic reference and bias control i1 i2 1 v cm clhi cllo in + in ? pwradj qp3 qp1 qp4 qp2 i3 i4 shdn qn1 qn3 qn2 qn4 v + out ? gnd 6417 bd out + 2 1 + ? v or over range detect
ltc6417 18 6417f a pplica t ions i n f or m a t ion circuit operation the ltc6417 is a low noise and low distortion fully dif - ferential unity gain adc driver with a C3db bandwidth spanning dc to 1.6ghz, a differential input impedance of 18.5k?, and a differential output impedance of 3. the ltc6417 is composed of a fully differential buffer with output common mode voltage control circuitry and high speed voltage-limiting clamps at the output. lowpass or bandpass filters are easily implemented with just a few external components. the ltc6417 is very flexible in terms of i/o coupling. it can be ac- or dc-coupled at the inputs, the outputs or both. when using the ltc6417 with dc-coupled inputs, best performance is obtained with an input common mode voltage between 1v and 1.5v. for ac-coupled operation, the ltc6417 will take the voltage applied to the v cm pin and use it to bias the inputs so that the output common mode voltage equals v cm , thus no external circuitry is needed. the v cm pin has been designed to directly interface with the v cm pin found on linear technologys high speed adc families. input impedance and matching the ltc6417 has a high differential input impedance of 18.5k?. the differential inputs may need to be terminated to a lower value impedance, e.g. 50, in order to provide an impedance match for the source. figure 1 shows input matching and single-ended to differential conversion using a 1:1 balun, while figure 2 shows a similar circuit using a 1:4 balun to achieve an additional 6db of voltage gain. these circuits provide a wideband impedance match. the balun and matching resistors must be placed close to the input pins in order to minimize the rejection due to input mismatch. in figures 1 and 2, the capacitor center- tapping the two input termination resistors improves high frequency common mode rejection. as an alternative to this wideband approach, a narrowband impedance match can be used at the inputs of the ltc6417 for frequency selection and/or noise reduction. figure 2. input termination for differential 50 input impedance using a 1:4 balun figure 1. input termination for differential 50 input impedance using a 1:1 balun ? ? v in in + in ? 8 9 24.9 0.1f 50 24.9 out ? 6417 f01 out + 18 19 ltc6417 0.1f 0.1f 0.1f 1:1 t1 maba-007159-000000 + ? 5 4 1 3 2 v in t1 tcm4-19+ in + in ? 8 9 out ? 6417 f02 out + 18 19 ltc6417 50 0.1f 100 + ? 100 0.1f 0.1f 0.1f 4 6 3 1
ltc6417 19 6417f a pplica t ions i n f or m a t ion the noise figure of the ltc6417 application circuit also depends upon the input termination. for example, the input 1:4 balun in figure 2 improves noise figure by add- ing 6db of voltage gain at the inputs. a trade-off between gain and noise is obvious when constant noise figure circle and constant gain circle are plotted within the same input smith chart. this technique can be used to determine the optimal source impedance for a given gain and noise requirement. output match and filter the ltc6417 provides an output resistance of 1.5 at each output. in most cases, the ltc6417 can be used to drive an adc without back termination but for testing purposes, figure 3 shows the ltc6417 driving a differ - ential 50 load impedance using a 1:1 balun. if output figure 4. output termination for differential 50 load using a 1:1 balun figure 3. ltc6417 with no back termination driving a 50 load using a 1:1 balun matching for the 1:1 balun is desired, resistors of 23.7 should be inserted in series with each ltc6417 output. this is shown in figure 4 where the ltc6417 is driving a differential 100 load impedance. as mentioned above, the ltc6417 can drive an adc with - out external output impedance matching, but improved performance can usually be obtained with the addition of a few components. figure 5 shows a 6th order bandpass filter with a 148mhz center frequency, C3db points of 85mhz and 210mhz used for driving the ltc2209 16-bit adc. in the passband the filter has less than 1 db ripple. this higher order filter has a sharp roll-off outside its passband, therefore it rejects noise and suppresses dis- tortion components in its stopband. to double the filter center frequency, halve the capacitor and inductor values, and maintain resistor values; this also doubles the filter bandwidth. ? ? t2 maba-007159-000000 in + in ? 8 9 out ? 6417 f03 out + 19 18 ltc6417 0.1f 0 50 0.1f 0 ? ? t2 maba-007159-000000 in + in ? 8 9 out ? 6417 f04 out + 18 19 ltc6417 0.1f 23.7 50 0.1f 23.7 4 5 3 1
ltc6417 20 6417f figure 5. dc1685a simplified schematic with suggested bandpass filter for driving an ltc2209 16-bit adc at 140mhz a pplica t ions i n f or m a t ion ?? 100 100 pwradj gnd shdn clhi v or 6417 f05 out + out ? 0.1f 0.01f 0.01f 5v 2.2f 3.3v v cm 2.2f 8 1,6, 11,16 3, 7,10, 17, 20, 21 5 12 15 14 2 9 19 18 t1 wbc4-14lb 10 10 r42 300 c45 18pf e3 75nh r43 300 1k r53 120 a in + a in ? pga = 0 ltc2209 in + v + in ? ltc6417 680pf clock (153.6mhz) 16 4 6 3 2 1 v cm c40 12pf c41 12pf e5 51nh c10 12pf c46 18pf e3 75nh r36 60.4 c43 27pf e1 51nh r12 60.4 c44 27pf e2 51nh 50 + ? 0 0 table 1. bandpass filter component values for different input frequencies input frequencies components 70mhz 140mhz 270mhz 380mhz r12 = r36 60.4 60.4 60.4 60.4 c43 = c44 56pf 27pf 15pf 12pf e1 = e2 100nh 51nh 27nh 18nh c41 47pf 12pf 12pf 10pf c10 = c40 13pf 12pf 3.3pf 2.7pf e5 100nh 51nh 27nh 18nh r42 = r43 300 300 300 300 r53 120 120 120 120 c45 = c46 39pf 18pf 10pf 8.2pf e3 = e4 150nh 75nh 39nh 27nh
ltc6417 21 6417f a pplica t ions i n f or m a t ion output common mode adjustment for ac-coupled applications, the output common mode voltage is set by the v cm pin. an internal buffer, as shown in figure 6, couples the voltage on the v cm pin to the inputs via high impedance resistors. because the input common mode voltage is approximately the same as the output common mode voltage, both are approximately equal to the voltage applied to the v cm pin. for dc-coupled applications, the internal v cm is overdriven by the input signal. the v cm pin has a thevenin equivalent resistance of 2.7k and can be overdriven by an external voltage. the v cm pin floats to a default voltage of 1.25v on a 5v supply. the output common mode voltage is capable of tracking v cm in a range from 0.29v to 2.25v on a 5.0v supply. the v cm pin can be floated, but it should always be bypassed close to the ltc6417 with a 0.1f bypass capacitor to gnd. when interfacing with a/d converters such as the ltc22xx families, the v cm pin can be connected to the v cm output pin of the adc, as shown in figure 5. clamping, the clhi pin and the v cm pin the clhi pin is used to set the high side clamp voltage of the high speed internal circuitry. this limits the single-ended maximum and minimum voltage excursion at each of the outputs. this feature is extremely important in applications with input signals having very large peak-to-average ratios such as cellular base station receivers. internal circuitry generates a symmetric low side clamp voltage with respect to the common mode voltage v cm (figures 7 and 8). the ltc6417 clamp control circuitry features two additional mechanisms. first, internally im- posed maximum swing of 2.5v and minimum swing of 0.2v ensure that the transistors do not go into deep saturation. this ensures a quick recovery after the clamps are released. second, if clhi voltage is less than v cm , internal cllo starts to track clhi. this limits output swing and protects output transistors. since the clamp response is on the order of 5ns to clamp and 1ns to release, clamp circuit becomes less effective at frequencies beyond 160mhz. figure 6. ltc6417 internal topology showing the common mode buffer biasing the inputs 6417 f06 x1 x1 1.5 10.8k v + in+ out+ out? in? gnd v cm 3.6k 9.25k 9.25k x1 1.5 ltc6417 figure 7. internal circuitry generating symmetric clamp voltages with respect to v cm figure 8. symmetric high- and low-side clamp voltages with respect to v cm 6417 f07 x1 ? + v + clhi clhi (int) cllo (int) gnd x2 v cm 9.6k 9.6k ltc6417 6417 f08 v cm clhi cllo
ltc6417 22 6417f a pplica t ions i n f or m a t ion the v or pin, as shown in figure 9, is internally connected to a current source sourcing 2ma, plus an internal 20k resistor pull-down to gnd. an internal clamp limits the maximum output to 3.4v. as soon as one of the inputs goes beyond the limits, and therefore engages one of the clamps, the output current, hence, the v or voltage goes to zero. the dynamic response of the v or pin can be ad- justed with an external resistor and an optional external capacitor. for a high speed operation, add a 50 resistor from v or to gnd, resulting in a high speed signal with 100mv swing. the pwradj pin the voltage applied to the pwradj pin scales the supply current and performance of the ltc6417. this is useful for reducing power consumption in applications where linearity of the ltc6417 exceeds the linearity of the other components in the system; hence ltc6417s linearity can be derated without effecting system performance. pwradj is a high impedance input. it has an input impedance of 14.5k. on a 5v supply, pwradj self-biases to 1.6v. for full power, simply connect pwradj to the positive supply v + . for minimum power, short the pwradj pin to gnd. the pwradj pin should be bypassed with a 0.1f capacitor as close to the ltc6417 as possible. ltc6417 performance vs pwradj can be found in the graphs. the shdn pin when pulled high, the shdn pin puts the ltc6417 in sleep mode, significantly reducing supply current. shdn is a high impedance input. it has an input impedance of 10.5k?. if the shdn pin is not driven with an external voltage, it floats down to the same potential as gnd, keeping the ltc6417 enabled. the shdn pin should be bypassed with a 0.1f capacitor as close to the ltc6417 as possible. in sleep mode, the input and output stages are turned off, but the input and output clamps are kept alive to protect the part against overvoltage. the supply current in sleep mode is only 24ma, instead of the typical 125ma. but should the clamps turn on, the current drawn from the supply can be as high as 180ma. if a very large signal arrives at the ltc6417, the voltages applied to the clhi and v cm pins will determine the maxi- mum and minimum output swing. once the input signal returns to the normal operating range, the ltc6417 returns to linear operation within 2ns. for dc-coupled operation, the common mode of the input signals might be different than the voltage on the v cm pin. the minimum swing will still be set by the voltages applied to the v cm and clhi pins. clhi is a high impedance input. it has an input impedance of 4.8k. on a 5v supply, clhi self-biases to 2.5v. to limit the signal swing to a subsequent stages power supply, e.g. an adc such as the ltc2165, simply connect clhi to the positive supply pin of the ltc2165. the clhi pin should be bypassed with a 0.1f capacitor as close to the ltc6417 as possible. the v or pin the v or , overrange pin signals an overrange condition when one or both inputs exceed the minimum or maximum signal swing limits set by the clhi and v cm pins. the ltc6417 v or pin can be used by a control system to limit the input power dynamically. this is very useful in applications where the overload response of the complete system would be too slow. figure 9. ltc6417 internal topology showing v or pin with pull-down resistor and clamp 6417 f09 v or 20k i cl 2ma ltc6417 gnd v +
ltc6417 23 6417f a pplica t ions i n f or m a t ion this can be avoided by following a few precautions when putting the ltc6417 in sleep mode: ? do not force the outputs below the inputs, this will turn the output stages on. ? either float clhi or tie it to v cc . this will allow a wider signal range at the inputs before the clamps are activated. ? maintain the inputs below clhi or 2.5v whichever is lower, other wise the input clamps will be activated. ? do not short v cm or the outputs to gnd, in either case the output clamps will turn on. current drawn from the supply can be as high as 180ma. ? float the outputs if possible. the outputs will be pulled down by internal resistors to v cm . heeding these precautions will protect the ltc6417 as well any part it is driving, while maintaining a low current consumption in sleep mode. noise and noise figure the ltc6417s differential input referred voltage and current noise densities are 1.5nv/ hz and 4.3pa/hz , respectively. before presenting a noise model, the circuit with the transformer in figure 10 will be simplified. in figure 11, the circuit is redrawn with the source impedance reflected to the secondary side of the transformer. the source impedance is multiplied by the impedance ratio m of the transformer. in figure 12, noise sources associated with the amplifier and resistors have been added. based on this noise model of the ltc6417, the total output noise power excluding the noise contribution of the source is: e 2 no = e 2 ni + i ni ? r eq ( ) 2 + i 2 r t ? r 2 eq = e 2 ni + i ni ? r eq ( ) 2 + 4kt r t ? r 2 eq where r eq = mr s ||r t is the equivalent impedance seen at the input of the ltc6417. the output noise power due to the noise of source resistance is given by: e 2 no(mr s ) = i 2 mr s ? r 2 eq = 4kt mr s ? r 2 eq noise figure (nf) is calculated from the ratio of these noise powers: nf = 10log 1 + e 2 no e 2 no(mr s ) ? ? ? ? ? ? ? ? figure 10. ltc6417 with a transformer 6417 f10 r t ltc6417 r s 1:m transformer figure 11. source resistance referred to the secondary 6417 f11 r t ltc6417 mr s figure 12. ltc6417 simplified noise model 6417 f12 r t i 2 ni e ni 2 e no 2 ltc6417 mr s i 2 mrs i 2 rt
ltc6417 24 6417f a pplica t ions i n f or m a t ion in most cases the termination resistor will be matched to the source resistance, e.g. r t = mr s . for the ltc6417 with a wide-band terminated transformer, a plot of output and input noise density and nf versus termination resistor is shown in figure 13. to get the best noise performance in the system, use the ltc6417 matched to a transformer with high impedance ratio. although the output noise density will be higher, noise figure will improve because of the additional gain realized in the transformer. an impedance ratio greater than 8 is not recommended, as the increased termination resistance with the ltc6417 input capacitance will limit signal bandwidth. consult table 2 for a quick estimate of the ltc6417s output noise density and nf for different transformer impedance ratios. measured nf numbers will be higher as the simple noise model does not take the insertion loss in the transformer into account. table 2. output noise density and nf of the ltc4617 with a wide-band terminated transformer, r s = 50? transformer impedance ratio m termination resistor r t () gain (v/v) output noise density e no (nv/hz) nf (db) 1 50 1.0 1.57 11.2 2 100 1.4 1.64 8.9 4 200 2.0 1.80 7.0 8 400 2.8 2.14 5.9 interfacing the ltc6417 to a/d converters the ltc6417 has been specially designed to interface directly with high speed a/d converters. it is possible to drive the adc directly from the ltc6417. in practice, however, better performance may be obtained by adding a few external components at the output of the ltc6417. figure 5 shows the ltc6417 driving an ltc2209 16-bit adc. the differential outputs of the ltc6417 are bandpass filtered, then drive the differential inputs of the ltc2209. in many applications, a filter like this is desirable to limit the wideband noise of the amplifier. this is especially true in high performance 16-bit designs. the minimum recommended network between the ltc6417 and the adc is simply two 10 series resistors, which are used to help eliminate resonances associated with the stray capacitance of pcb traces and the stray inductance of the internal bond wires at the adc input pins and the driver output pins. single-ended signals the ltc6417 has not been designed to convert single- ended signals to differential signals. a single-ended input signal can be converted to a differential signal via a balun connected to the inputs of the ltc6417. figure 5 shows the ltc6417 driven by a 1:4 transformer which provides 6db of voltage gain while also performing a single-ended to differential conversion. power supply considerations for best linearity, the ltc6417 should have a positive supply of v + = 5v. for esd protection, the ltc6417 has an internal edge-triggered supply voltage clamp. the timing mechanism of the clamp enables the ltc6417s protection circuit during esd events. this internal clamp can also be activated by voltage overshoot and rapid slew rate on the positive supply v + pin. the ltc6417 should not be hot-plugged into a powered socket because there is a risk of activating this internal esd clamp circuit. bypass capacitors of 680pf and 0.1f should be connected to the v + pin, as close as possible to the ltc6417. interfacing the ltc6417 with active mixers for ultrawide if bandwidth the ltc6417 is an excellent interface amplifier for use with active downconverting mixers like the ltc5567. by using figure 13. ltc4617 output and input noise density and nf vs termination resistance termination resistance () e no (nv/ hz) nf (db) 6417 f13 50 150 400 100 200 300 350 250 2.3 2.1 1.1 1.3 0.9 1.7 1.9 1.5 0.7 12 11 6 7 5 9 10 8 4 nf e no e ni
ltc6417 25 6417f a pplica t ions i n f or m a t ion the ltc6417 as a post-amplifier for the ltc5567, it is pos - sible to achieve if bandwidths in excess of 500mhz, while adding bandpass filtering. a key to achieving this extremely wide if bandwidth is the use of pre-emphasis inductors in series with the ltc6417 inputs to compensate for the inherent rolloff caused by the ltc6417 input capacitance interacting with the interface impedance. in the example seen in figure 14, a value of 33nh for each pre-emphasis inductor gives excellent wideband performance. figure 15 shows performance for various values of l. for l = 33nh, overall conversion gain remains within 1db from 90mhz to 590mhz, resulting in 500mhz of if bandwidth. test circuits due to the fully differential design of the ltc6417 and its usefulness in applications both with and without adcs, two test circuits have been used to generate the information in this data sheet. test circuit a is dc1660b, a two-port demonstration circuit for the ltc6417. the board layout and the schematic are shown in figures 16 and 17. these circuits include a 1:4 input balun and a 1:1 output balun for single-ended-to-differential conversion, allowing direct analysis using a 2-port network analyzer. including the input and output baluns, the C3db bandwidth is approximately 600mhz. a 1:4 input balun before the ltc6417 inputs provides 6db of voltage gain, but results in better noise figure performance compared to a 1:1 input balun. noise figure measurements for both input baluns can be found in the graphs. test circuit b is dc1685a. it consists of an ltc6417 driving an ltc2209 16-bit 153.6msps adc. it is intended for use in conjunction with dc890b (computer interface board) and proprietary linear technology evaluation software to evaluate the performance of both parts together. both the dc1685a board layout and the schematic can be seen figures 18 and 19. if frequency (mhz) g c (db) 6417 f15 40 140 740 340 640540440 240 2 1 0 ?5 ?4 ?6 ?2 ?1 ?3 ?7 l = 33nh l = 18nh l = 0nh lpf figure 14 figure 15 rf 1.69ghz to 2.39ghz lo 1.65ghz 6417 f14 127 l 1nf 23.2 1nf ltc6417 127 390n 390n 10nf 249 v cc if+ if? 249 l 1nf if out 50 1:1 1nf 23.2 ltc5567
ltc6417 26 6417f a pplica t ions i n f or m a t ion figure 16. demo board dc1660b layout
ltc6417 27 6417f figure 17. demo board dc1660b schematic (test circuit a) a pplica t ions i n f or m a t ion 5 5 4 4 3 3 2 2 1 1 d d c c b b a a in- gnd v+ 4.75v - 5.25v pwradj cl hi shut down vcm in+ out+ out- or 1. all resistors and capacitors are 0402 note: unless otherwise specified v+ v+ v+ v+ v+ revision history description date approved eco rev john c. 2nd prototype 2 09-12-11 __ revision history description date approved eco rev john c. 2nd prototype 2 09-12-11 __ revision history description date approved eco rev john c. 2nd prototype 2 09-12-11 __ size date: ic no. rev. sheet of title: approvals pcb des. app eng. technology fax: (408)434-0507 milpitas, ca 95035 phone: (408)432-1900 1630 mccarthy blvd. ltc confidential-for customer use only customer notice linear technology has made a best effort to design a circuit that meets customer-supplied specifications ; however, it remains the customer's responsibility t o verify proper and reliable operation in the actual application. component substitution and printed circuit board layout may significantly affect circu it performance or reliability. contact linear technology applications engineering for assistance. this circuit is proprietary to linear technology an d schematic supplied for use with linear technology parts. scale = none www.linear.com 2 monday, september 12, 2011 11 adc buffer lt john c. n/a ltc6417cudc demo circuit 1660b size date: ic no. rev. sheet of title: approvals pcb des. app eng. technology fax: (408)434-0507 milpitas, ca 95035 phone: (408)432-1900 1630 mccarthy blvd. ltc confidential-for customer use only customer notice linear technology has made a best effort to design a circuit that meets customer-supplied specifications ; however, it remains the customer's responsibility t o verify proper and reliable operation in the actual application. component substitution and printed circuit board layout may significantly affect circu it performance or reliability. contact linear technology applications engineering for assistance. this circuit is proprietary to linear technology an d schematic supplied for use with linear technology parts. scale = none www.linear.com 2 monday, september 12, 2011 11 adc buffer lt john c. n/a ltc6417cudc demo circuit 1660b size date: ic no. rev. sheet of title: approvals pcb des. app eng. technology fax: (408)434-0507 milpitas, ca 95035 phone: (408)432-1900 1630 mccarthy blvd. ltc confidential-for customer use only customer notice linear technology has made a best effort to design a circuit that meets customer-supplied specifications ; however, it remains the customer's responsibility t o verify proper and reliable operation in the actual application. component substitution and printed circuit board layout may significantly affect circu it performance or reliability. contact linear technology applications engineering for assistance. this circuit is proprietary to linear technology an d schematic supplied for use with linear technology parts. scale = none www.linear.com 2 monday, september 12, 2011 11 adc buffer lt john c. n/a ltc6417cudc demo circuit 1660b c21 0.1uf c21 0.1uf j5 j5 c3 0.1uf c3 0.1uf e7 e7 j3 j3 c18 680pf c18 680pf e4 e4 r5 0 r5 0 j4 j4 j2 j2 c2 680pf c2 680pf c9 0.1uf c9 0.1uf c1 0.1uf c1 0.1uf e2 e2 u1 ltc6417cudc u1 ltc6417cudc v+ 6 gnd 7 in+ 8 in- 9 gnd 10 gnd 17 out- 18 out+ 19 gnd 20 v+ 11 pwradj 5 nc 4 gnd 3 cl hi 2 v+ 1 shutdown 12 nc 13 or 14 vcm 15 v+ 16 gnd 21 c17 0.1uf c17 0.1uf c7 0.1uf c7 0.1uf t1 tcm4-19+ t1 tcm4-19+ 1 5 3 4 2 j1 j1 e5 e5 r1 0 r1 0 c24 0.1uf c24 0.1uf c22 680pf c22 680pf c6 opt 0603 c6 opt 0603 r3 0 r3 0 r2 100 r2 100 c8 opt 0603 c8 opt 0603 c16 680pf c16 680pf c11 0.1uf 0603 c11 0.1uf 0603 r8 opt r8 opt c20 0.1uf c20 0.1uf c13 0.1uf c13 0.1uf c4 0.1uf c4 0.1uf r4 0 r4 0 c12 0.1uf 0603 c12 0.1uf 0603 r6 100 r6 100 c5 0.1uf c5 0.1uf c15 0.1uf c15 0.1uf c14 0.1uf c14 0.1uf c23 opt 0603 c23 opt 0603 t2 maba-007159-000000 t2 maba-007159-000000 5 4 3 1 2 c19 0.1uf c19 0.1uf r7 opt r7 opt e1 e1 c10 0.1uf c10 0.1uf e3 e3
ltc6417 28 6417f figure 18. demo board dc1685a layout a pplica t ions i n f or m a t ion
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???????????????????????????????????????????????? ????????????????????????????????????????????????????? ??????????????????????????????????????????? ??????????????????????????????????????????????????? ???????????????????????????????????????????????????? ????????? ?????????????????????????????????????????????? ???????????? ?????????????? ? ?????????????????????? ?? ???????????????????????? ????? ???????? ??? ?????????????????????? ?????????????????? ??? ? ??? ? ??? ???? ??? ???? ??? ??? ??? ??? ?? ?? ??? ?? ??? ???? ?? ?? ??? ?? ??? ???? ? ? ? ? ? ? ?? ???? ???? ?? ???? ???? ??? ????? ??? ????? ?? ????? ?? ????? ??? ??? ??? ??? ??? ???? ??? ???? ??? ?? ??? ?? ?? ????? ???? ?? ????? ???? ??? ???? ??? ???? ?? ????????? ?? ????????? ? ? ? ? ? ?? ?????????? ?? ?????????? ????? ? ??? ? ??? ? ??? ? ??? ? ??? ? ??? ? ???? ? ???? ? ??? ?? ??? ?? ???? ?? ???? ?? ??? ?? ??? ?? ??? ?? ??? ?? ??? ?? ???? ?? ???? ?? ??????? ?? ??????? ?? ??????? ?? ??????? ?? ??????? ?? ??????? ?? ??????? ?? ??????? ?? ??????? ?? ??????? ?? ???? ?? ???? ?? ???????? ?? ???????? ?? ???????? ?? ???????? ?? ???????? ?? ???????? ?? ??????????? ?? ??????????????? ?? ??????????? ?? ??????? ?? ??????? ?? ??????? ?? ???????? ?? ???????? ?? ???????? ?? ???????? ?? ???? ?? ???? ?? ???????? ?? ???????? ?? ???????? ?? ????????? ?? ????????? ?? ????????? ?? ????????? ?? ????????? ?? ???????? ?? ???????? ?? ???? ?? ???? ?? ???? ?? ??? ?? ??? ?? ?? ????? ?? ????? ??? ??? ???? ??? ??? ???? ??? ????? ??? ????? ?? ???? ?? ?? ???? ?? ??? ????? ???? ??? ????? ???? ?? ???? ?? ?? ???? ?? ?? ?????? ???? ?? ?????? ???? ??? ??? ?? ???? ??? ??? ?? ???? ??? ????? ???? ??? ????? ???? ??? ????? ?? ??? ????? ?? ??? ??? ???? ??? ??? ???? ??? ????? ???? ??? ????? ???? ??? ???? ??? ???? ??? ????????? ?????????????? ??? ????????? ?????????????? ??? ????? ??? ????? ??? ??? ??? ??? ??? ????? ??? ????? ?? ????? ???? ?? ????? ???? ??? ????? ??? ????? ??? ??????? ??? ??????? ??? ????? ???? ??? ????? ???? ?? ???? ???? ?? ???? ???? ??? ????? ???? ??? ????? ???? ?? ?????????????? ?? ?????????????? ?? ???? ???? ?? ???? ???? ?? ?????????? ?? ?????????? ???? ? ??? ? ?? ? ??? ? ????? ? ????? ? ??? ? ???? ? ??? ?? ??? ?? ?? ?????? ???? ?? ?????? ???? ??? ??? ??? ??? ??? ???? ??? ???? ?? ????? ???? ?? ????? ???? ??? ????? ??? ????? ??? ? ??? ? ??? ????? ??? ??? ????? ??? ?? ???? ???? ?? ???? ???? ??? ????? ??? ????? ?? ?????????????? ?? ?????????????? ??? ??????? ??? ??????? ?? ??? ?? ???? ????? ?? ??? ?? ???? ????? ?? ??? ?? ??? ??? ???? ??? ???? ??? ??? ???? ??? ??? ???? ??? ????? ??? ????? ?? ????? ?? ????? ?? ???? ?? ?? ???? ?? ?? ?????????????????? ?? ?????????????????? ? ? ? ? ? ??? ????? ??? ????? ??? ?? ???? ??? ?? ???? ??? ? ??? ? ??? ????? ??? ????? ?? ???? ?? ?? ???? ?? ??? ????? ??? ??? ????? ??? ??? ????? ??? ????? ?? ?? ?? ?? ??? ???? ??? ???? ??? ??? ??? ??? ?? ????? ???? ?? ????? ???? ??? ????? ??? ????? ?? ??????????? ?? ??????????? ?? ? ??? ? ??? ? ?? ? ?????? ? ?? ? ??? ? ???? ?? ??? ? ??? ?? ?? ?? ???? ?? ?? ?? ??? ?? ??? ?? ?? ?? ??? ?? ??? ?? ???? ?? ??? ? ??? ?? ??? ????? ??? ????? ??? ????? ??? ????? ??? ????? ??? ????? ?? ??? ??? ??? ???? ?? ??? ??? ??? ???? ? ? ? ? ? ? ??? ????? ??? ????? ?? ?? ? ? ? ? ? ? ?? ???? ???? ?? ???? ???? ??? ? ??? ? ?? ?????? ???? ?? ?????? ???? ??? ??? ???? ??? ??? ???? ?? ????? ?? ????? ??? ?? ???? ??? ?? ???? ??? ????? ??? ????? ?? ???????????? ?? ???????????? ??? ???? ??? ???? ?? ?? ??? ??? ???? ?????? ?? ?? ??? ??? ???? ?????? ? ? ? ? ? ? ??? ????? ??? ????? ?? ?????????????? ?? ?????????????? ??? ???? ??? ???? ?? ????? ???? ?? ????? ???? ??? ?????? ??? ?????? ??? ? ??? ? ?? ??? ?? ???
ltc6417 30 6417f a pplica t ions i n f or m a t ion figure 19 (continued). demo board dc1685a schematic (test circuit b) 5 5 4 4 3 3 2 2 1 1 e e d d c c b b a a ???????? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ??? ??? ????? ????? ?? ?? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ?? ??? ????? ???????? ?? ????? ???????? ????? ????? ?? ???????? ???? ???? ???? ???? ???? ????? ?????? ???? ????? ?? ?????? ????????? ???????? ???????? technology ?????????????????? ?????????????????? ???????????????????? ??????????????????? ?????????????????????????????????????? ??????????????? ???????????????????????????????????????????????????? ???????????????????????????????????????????????????? ???????????????????????????????????????????????????? ?????????????????????????????????????????????????? ???????????????????????????????????????????????? ????????????????????????????????????????????????????? ??????????????????????????????????????????? ??????????????????????????????????????????????????? ???????????????????????????????????????????????????? ????????? ?????????????????????????????????????????????? ???????????? ?????????????? ? ???????????????????? ?? ???????????????????????? ????? ???????? ??? ?????????????????????? ?????????????????? ???? ????? ?????? ???? ????? ?? ?????? ????????? ???????? ???????? technology ?????????????????? ?????????????????? ???????????????????? ??????????????????? ?????????????????????????????????????? ??????????????? ???????????????????????????????????????????????????? ???????????????????????????????????????????????????? ???????????????????????????????????????????????????? ?????????????????????????????????????????????????? ???????????????????????????????????????????????? ????????????????????????????????????????????????????? ??????????????????????????????????????????? ??????????????????????????????????????????????????? ???????????????????????????????????????????????????? ????????? ?????????????????????????????????????????????? ???????????? ?????????????? ? ???????????????????? ?? ???????????????????????? ????? ???????? ??? ?????????????????????? ?????????????????? ???? ????? ?????? ???? ????? ?? ?????? ????????? ???????? ???????? technology ?????????????????? ?????????????????? ???????????????????? ??????????????????? ?????????????????????????????????????? ??????????????? ???????????????????????????????????????????????????? ???????????????????????????????????????????????????? ???????????????????????????????????????????????????? ?????????????????????????????????????????????????? ???????????????????????????????????????????????? ????????????????????????????????????????????????????? ??????????????????????????????????????????? ??????????????????????????????????????????????????? ???????????????????????????????????????????????????? ????????? ?????????????????????????????????????????????? ???????????? ?????????????? ? ???????????????????? ?? ???????????????????????? ????? ???????? ??? ?????????????????????? ?????????????????? ??? ????? ??? ????? ??? ??? ???? ??? ??? ???? ?? ?????????? ?? ?????????? ?????? ?? ??? ? ??? ? ????? ? ????? ? ????? ? ????? ? ????? ? ????? ? ????? ? ????? ?? ????? ?? ??? ?? ?? ?? ????? ?? ????? ?? ????? ?? ????? ?? ????? ?? ????? ?? ????? ?? ????? ?? ????? ?? ??? ?? ??? ?? ??? ?? ??? ?? ????? ?? ?????? ?? ?????? ?? ?????? ?? ?????? ?? ?????? ?? ?????? ?? ??? ?? ?????? ?? ??? ?? ?????? ?? ?????? ?? ?????? ?? ?????? ?? ?????? ?? ?????? ?? ?????? ?? ?????? ?? ????? ?? ??? ?? ??? ?? ??? ????? ??? ????? ??? ??? ???? ??? ??? ???? ??? ????? ??? ????? ??? ????? ??? ????? ??? ??? ???? ??? ??? ???? ??? ????? ?? ??? ????? ?? ??? ??? ???? ??? ??? ???? ??? ????? ??? ????? ??? ??? ???? ??? ??? ???? ??? ????? ??? ????? ??? ??? ???? ??? ??? ???? ??? ??? ???? ??? ??? ???? ?? ?????????? ?? ?????????? ?????? ?? ??? ? ??? ? ????? ? ????? ? ????? ? ????? ? ????? ? ????? ? ????? ? ????? ?? ????? ?? ??? ?? ?? ?? ????? ?? ????? ?? ????? ?? ????? ?? ????? ?? ????? ?? ????? ?? ????? ?? ????? ?? ??? ?? ??? ?? ??? ?? ??? ?? ????? ?? ?????? ?? ?????? ?? ?????? ?? ?????? ?? ?????? ?? ?????? ?? ??? ?? ?????? ?? ??? ?? ?????? ?? ?????? ?? ?????? ?? ?????? ?? ?????? ?? ?????? ?? ?????? ?? ?????? ?? ????? ?? ??? ?? ??? ?? ??? ???????????? ??? ???????????? ? ? ? ? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ??? ? ? ? ? ? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ??? ??? ???? ??? ??? ???? ??? ??? ???? ??? ??? ???? ??? ????? ??? ????? ??? ??? ???? ??? ??? ???? ??? ???? ??? ???? ??? ????? ?? ??? ????? ?? ??? ??? ???? ??? ??? ???? ??? ??? ???? ??? ??? ???? ??? ????? ?? ??? ????? ?? ??? ??? ???? ??? ??? ???? ??? ????? ??? ????? ??? ??? ???? ??? ??? ???? ??? ??? ???? ??? ??? ???? ??? ????? ??? ????? ??? ??? ???? ??? ??? ???? ?? ???????????? ?? ???????????? ?? ? ?? ? ?? ? ??? ? ??? ? ?? ? ??? ? ??? ?
ltc6417 31 6417f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion 3.00 0.10 1.50 ref 4.00 0.10 note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 19 20 1 2 bottom view?exposed pad 2.50 ref 0.75 0.05 r = 0.115 typ pin 1 notch r = 0.20 or 0.25 45 chamfer 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (udc20) qfn 1106 rev ? recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 2.50 ref 3.10 0.05 4.50 0.05 1.50 ref 2.10 0.05 3.50 0.05 package outline r = 0.05 typ 1.65 0.10 2.65 0.10 1.65 0.05 2.65 0.05 0.50 bsc udc package 20-lead plastic qfn (3mm 4mm) (reference ltc dwg # 05-08-1742 rev ?) please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
ltc6417 32 6417f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2012 lt 0712 ? printed in usa r ela t e d p ar t s typical a pplica t ion part number description comments fixed gain if amplifiers/adc drivers ltc6400-8/LTC6400-14/ ltc6400-20/ltc6400-26 1.8ghz low noise, low distortion differential adc drivers C71dbc im3 at 240mhz 2v p-p composite, i s = 90ma, a v = 8db, 14db, 20db, 26db ltc6420-20 dual 1.8ghz low noise, low distortion differential adc drivers dual version of the ltc6400-20, a v = 8db, 14db, 20db, 26db ltc6401-8/ltc6401-14/ ltc6401-20/ltc6401-26 1.3ghz low noise, low distortion differential adc drivers C74dbc im3 at 140mhz 2v p-p composite, i s = 50ma, a v = 8db, 14db, 20db, 26db ltc6421-20 dual 1.3ghz low noise, low distortion differential adc drivers dual version of the ltc6401-20, a v = 8db, 14db, 20db, 26db if amplifiers/adc drivers with variable gain ltc6412 800mhz, 31db range analog-controlled vga continuously adjustable gain control, C14db to 17db linear-in-db gain range lt5554 high dynamic range 7-bit digitally controlled if vga/adc driver oip3 = 46dbm at 200mhz, gain range 1.725 to 17.6db 0.125db steps lt5514 ultra-low distortion if amplifier/adc driver with digitally controlled gain oip3 = 47dbm at 100mhz, gain range 10.5db to 33db 1.5db steps lt5524 low distortion if amplifier/adc driver with digitally controlled gain oip3 = 40dbm at 100mhz, gain range 4.5db to 37db 1.5db steps baseband differential amplifiers lt6416 2ghz low noise differential 16-bit adc buffer C84dbc im3 at 160mhz 2v p-p composite, a v = 1, e n = 1.8nv/ hz, 42ma ltc6409 10ghz 1.1nvhz adc driver ac- or dc-coupled 0mhz to 100mhz ltc6406 3ghz rail-to-rail input differential amplifier/ adc driver C65dbc im3 at 50mhz 2v p-p composite, rail-to-rail inputs, e n = 1.6nv/ hz, 18ma ltc6404-1/ltc6404-2/ ltc6404-4 low noise rail-to-rail output differential amplifier/adc driver 16-bit snr and sfdr at 10mhz, rail-to-rail outputs, e n = 1.5nv/ hz, ltc6404-1 is unity-gain stable, ltc6404-2 is gain-of-2 stable ltc6403-1 low noise rail-to-rail output differential amplifier/adc driver 16-bit snr and sfdr at 3mhz, rail-to-rail outputs, e n = 2.8nv/ hz adcs ltc2209 16-bit 160msps adc 77.3dbfs noise floor, 100db sfdr ltc2208 16-bit 130msps adc 78dbfs noise floor, 100db sfdr dc1685a simplified schematic with suggested output termination for driving an ltc2209 16-bit adc at 140mhz ?? 100 100 pwradj gnd shdn clhi v or 6417 ta02 out + out ? 0.1f 0.01f 0.01f 5v 2.2f 3.3v v cm 2.2f 8 1,6, 11,16 3, 7,10, 17, 20, 21 5 12 15 14 2 9 19 18 t1 wbc4-14lb 10 10 r42 300 c45 18pf e3 75nh r43 300 1k r53 120 a in + a in ? pga = 0 ltc2209 in + v + in ? ltc6417 680pf clock (153.6mhz) 16 4 6 3 2 1 v cm c40 12pf c41 12pf e5 51nh c10 12pf c46 18pf e3 75nh r36 60.4 c43 27pf e1 51nh r12 60.4 c44 27pf e2 51nh 50 + ?

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